1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a backbias voltage (VBB) generation circuit and a method of generating backbias voltage corresponding to the high frequency in a semiconductor memory device.
2. Description of the Related Art
In a semiconductor memory device, a backbias voltage is a voltage lower than an external minimum voltage and is used for the following benefits:
First, the backbias voltage VBB prevents a PN junction in a memory chip from being forward-biased, which would cause a loss of data in memory cells or latch-up phenomena. Even if the data signal applied to an input terminal does not meet the desired level, a PN diode does not turn on when a backbias voltage is applied. Thus, electrons of the input terminal are not injected into the P-well.
Second, the circuit operation is stabilized by reducing the threshold voltage fluctuation of a MOS transistor caused by the body effect. If a backbias voltage VBB is applied, the threshold voltage is less affected by the source potential change. Thus, a backbias voltage VBB reduces the variation in the threshold voltage and, in turn, can reduce the voltage applied to the wordline, which increases the reliability of a device.
Third, the backbias voltage VBB increases a threshold voltage of a parasitic MOS transistor. The increased threshold voltage of the parasitic MOS transistor reduces the concentration of a channel stop impurity under a field oxide layer, which reduces the possibility of junction breakdown and current leakage.
Fourth, the backbias voltage VBB reduces PN junction capacitance formed between an N.sup.+ region (drain and source) of an NMOS and P-well, so that the semiconductor memory device circuit can operate at a higher speed. The reduction in the PN junction capacitance reduces the parasitic capacitance of bit line contact and increases the data flow transmitted to the bit line.
One type of backbias voltage generation circuit is disclosed in U.S. Pat. No. 5,157,278. The backbias voltage generation circuit of the U.S. Pat. No. 5,157,278, as shown in FIG. 1, detects a backbias voltage and then drives a self-oscillating circuit to thereby generate the backbias voltage. One pumping circuit operates regardless of whether the device is in a standby mode (in which a memory neither reads nor writes) or in an active mode (in which the memory reads or writes).
However, the backbias voltage generation circuit disclosed in U.S. Pat. No. 5,157,278 does not sufficiently compensate for a semiconductor device's substrate current generated while in an active mode. Instead, the backbias voltage generation circuit disclosed in the U.S. Pat. No. 5,157,278 employs a small capacity pump driver in order to minimize the current consumption in a standby mode.
A similar backbias voltage generation circuit disclosed in U.S. Pat. No. 4,455,628 and shown in FIG. 2, drives a pump driver by a self-oscillating circuit operating without a backbias voltage detecting circuit. The pump is driven when a row address strobe signal (/RAS) and a column address strobe signal (/CAS) are activated.
The prior art backbias voltage generation circuits disclosed in both U.S. Pat. Nos. 5,157,278 and 4,455,628 also enables the self-oscillating circuit and drives the pump driver by detecting the backbias voltage or the activation of /RAS and /CAS, which causes the pumping operation to last longer than the active period of each row. Thus, the pump driver does not have sufficient temporal margins between one pumping operation and the next pumping operation, which increases the backbias voltage fluctuation.